Our Book uses "Silos"
Eng. A.Seliman recommended Active-HDL

but Both are commercial

So I've found 4 Open-source Verilog Simulators

1. GPL Cver by Pragmatic C
   Supported Languages: V2001
   This is a GPL open-source simulator with many performance features turned off. These features can be enabled for a fee. It is a pure simulator.
   Download
   
   
2. Icarus Verilog by Stephen Williams
   Supported Languages: V2001
   This simulator is not fully IEEE compliant.
   Download
   
   
3. Verilator by Veripool
   Supported Languages: V2001, V2005, minimal SV2005
   This is a very high speed open-source simulator that compiles synthesizable Verilog to C++/SystemC.
   Download
   
   
4. VeriWell by Elliot Mednick
   Supported Languages: V1995
   This simulator used to be commercial, but has recently become GPL open-source. Compliance with 1364 is not well documented. It is not fully compliant with IEEE 1364-1995.
   Download

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thanks ya tamer ... ana kont nawy ageb el silos mn Eng.Soliman bokra
delwa2ty lesa bardo hageb el silos mn Eng.Soliman bokra bs odamy options tanya

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Muhammad Ahmad Daif
4th year <matbsolesh b3en radya ... da ana tale3 3enya>
Moderator of Networks & Internet

When Engineers have sense of humor

thxxxx tamer

elly e7na hnsht3'al 3leh f el kolya msh silos f el kolya hnsht3'al 3la ActiveHDL
ana esht3'alt 3leah bas 7aset eno sa3b w 3'els 7aba

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Thanks, Tamer

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“Use whatever floats your boat!”
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Osama Gamal M. Attia
4th Year CSE
My Blog